Analysis and design of an improved full adder

Thesis of Master of Electrical Engineering (M.Sc)

Trend: Electronics

Abstract:

Increasing demand for portable systems has led the electronics industry to pay special attention to power consumption as an important criterion. Adders are important elements in many digital systems. For this reason, various digital collectors have been proposed in the current era, each of which has specific advantages and disadvantages. In this thesis, a structure for all dynamic adders is presented. This structure is designed by NP-CMOS and domino technique and dynamic logic principles. At the same time, the proposed structure has an acceptable power consumption and a suitable performance speed. For the purpose of comparison, this circuit was selected from among the many resources available in the field of all-collector circuit design, according to the number of references in other articles, and in terms of power consumption, delay, and PDP, they were compared with each other. The circuits in this thesis are all simulated in the same conditions by HSPICE software, with 180 nm technology. The simulation results show the superiority of the proposed adders compared to other models.

Key words: full adder, PDP, domino logic, NP CMOS logic, dynamic logic

Looking at the history of electronics, it can be seen that one of the primary reasons for the advancement of technology is the need of future generations to use new and more complex technologies. Digital circuits [1] also have advantages over analog circuits [2] due to their simplicity in design, the ability to implement them with cheap technologies, and lower power consumption (Navi, Moaiyeri, & Mirzaee, 2009). For this reason, along with the advancement of technology, energy consumption was also improved in circuits, including CMOS circuits. But the internal functioning of each may be different from the other. Therefore, one of the influencing factors in the circuit performance is the way the circuit is designed. Considering that each circuit is made of various components. One of the important components in some circuits, which causes a change in the performance of the circuit with small changes, is the adder [3] (Sadighi, Valizadeh, & Mehdipour, 2013). The adder circuit is one of the basic building blocks of many VLSI [4] systems, such as microprocessors and various processors (Sharifi, 2019). Since the features of adder blocks and other blocks determine the performance of the VLSI system, the main goal of designers is to optimize these blocks. Among the factors that optimize the relevant blocks are new designs in accordance with the advancement of new technology.

In the design of an all adder[5], one of the main goals is to achieve high speed. and generally have a good performance. Designing a full adder with a simple structure and limited power consumption can play a good role in simplifying digital circuits. There are certain criteria for better design of all collectors. The most important criterion is the application of the circuit. Other criteria can be mentioned as low power consumption [6], high speed [7] and simplicity of the circuit, which these criteria can be considered as components of the application criteria.

One of the most essential applications of all adders is in personal communication and computing devices (Moghadam, 2010). Considering that nowadays these devices are almost portable and fully available, the main concern is to increase the battery life and reduce the need for recharging (R. Faghih Mirzaee, 2010). Increasing the performance of a collector is directly related to the improvement of system performance. Therefore, many researchers are looking for ways to reduce power consumption. In electronics, the use of two logics, dynamic[8] and static[9] play a major role. Dynamic logic circuits also offer certain advantages over static logic circuits. Static logic circuits enable the implementation of logic functions based on the static behavior of pMOS and nMOS structures. In other words, each static gate produces its output in proportion to the applied input voltage after a specific delay [10] has passed, and maintains its output level as long as the supply voltage is maintained (Mozhari & Harandi, 2012) (Mano, 1979). But the performance of all dynamic logic gates is based on temporary storage of charge in node capacitors.As a result, dynamic logic circuits need alternating clock signals [11], [12] to control the updating of electric charge. And another important point is that the implementation of dynamic logic of complex functions requires a smaller silicon area [13] than the implementation of static logic. And since the power consumption increases with the capacity of parasitic capacitors, dynamic circuits in many cases consume less power compared to static circuits due to having a smaller area (Mozaheri & Harandi, 2012). But in addition to having the stated advantages, dynamic logic also has disadvantages, such as the fact that CMOS dynamic logic classes driven by a single-phase clock cannot be closed sequentially in their simple form. This problem can be solved by good solutions and the development of appropriate techniques such as domino logic [14] and NP-COMS [15]. fixed it By using dynamic logic instead of static logic, the number of transistors [16] used to realize any complex logic function can be reduced in a specific way (Sahib al-Zamani, Fathi, & Safaei, 1387).

The purpose of this thesis is to examine dynamic logic circuits in the full adder cell and to present a proposed structure and also to present some suggested circuits.

In this regard, while reviewing the presented adders, other adders are also have been investigated, all of which have been simulated using HSPICE software. The structure of the thesis is as follows: The second chapter deals with the concepts and parameters used in circuit design. In the third chapter, some logics of designing digital circuits are stated. And among the many sources in the field of design of dynamic full-adder circuits, some of them have been selected for comparison. In the fourth chapter, the proposed structure and several circuits of the full adder are presented, in the rest of this chapter, all the adders mentioned in this thesis have been simulated and compared in the same conditions by the HSPICE software. And finally, the fifth chapter deals with the conclusion.

Introduction:

In this chapter, the importance of all adders in the design of digital circuits and its effect will be discussed, and the types of digital adder structure such as half adder and full adder are introduced and the important parameters in the design of these circuits are stated. And they are considered the basic element in many computing circuits (Foroutan, Navi, & Haghparast, 2008). Today, with the widespread increase in the use of electronic devices; The need for collectors has also increased. The better quality features the collectors have; Its direct effect is evident in the used device, and as a result, the device will be popular with the public (J.Wang, 1994). For this reason, the provision of new structures for this circuit has attracted the attention of integrated circuit designers. The main goal in the design of the digital adder is to increase the speed and reduce the power consumption. 2-3- The structure of the digital adder: Digital computers perform various information processing tasks (Mano, 1979). Mathematical operations can be mentioned among their most used tasks. The most basic mathematical operation is the addition of two binary numbers. This simple addition consists of four operations according to equation (2-1). The first three operations of the sum produce a number. But the third operation of the sum is a two-digit number. The most valuable result of this sum is called the numerical value [17]. When we add two multi-bit numbers together, the digit resulting from the addition of two bits must be added with the higher value digits. The combined circuit used to add two bits is called a half-adder [18]. An adder that adds three bits together (two bits and the previous digit) is called a full adder [19]. A binary adder is a combinational circuit that performs the mathematical operation of addition on binary numbers. The sequential connection of n all full adders gives a binary adder for two n-bit numbers. Equation (2-1) 0=0+0, 1=0+1, 1=1+1, 10=1+1 2-3-1-adder The addition operation is one of the four main operations in digital circuits. In logical circuits, addition is done in two ways: full adder and half adder. 2-3-1-1-half adder As mentioned, a single bit half adder performs addition between two bits.